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Features
* * * *
High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells - 48 Flip-flops - Two per Macrocell - 72 Sum Terms - All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback Backward Compatible with ATV2500B/BQ and ATV2500H Software Advanced Electrically-erasable Technology - Reprogrammable - 100% Tested 44-lead Surface Mount Package and DIP Package Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously 8 Synchronous Product Terms Individual Asynchronous Reset per Macrocell OE Control per Macrocell Functionality Equivalent to ATV2500B/BQ and ATV2500H 2000V ESD Protection Security Fuse Feature to Protect the Code Commercial and Industrial Temperature Range Offered 10 Year Data Retention Pin Keeper Option 200 mA Latch-up Immunity
* * * * * * * * * * * * * * * * *
ATF2500C CPLD Family Datasheet ATF2500C
Block Diagram
Pin Configurations
Pin Name IN CLK/IN I/O I/O 0,2,4... I/O 1,3,5... GND VCC Function Logic Inputs Pin Clock and Input Bi-directional Buffers "Even" I/O Buffers "Odd" I/O Buffers Ground +5V Supply
CLK/IN IN IN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 IN IN IN IN
DIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 IN IN IN IN I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 IN IN IN
PLCC/LCC/JLCC
I/O1 I/O0 GND IN IN CLK/IN IN IN IN IN I/O6 I/O12 IN IN IN IN IN IN IN GND I/O18 I/O19 18 19 20 21 22 23 24 25 26 27 28 I/O2 I/O3 I/O4 I/O5 VCC VCC I/O17 I/O16 I/O15 I/O14 I/O13 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O7 I/O8 I/O9 I/O10 I/O11 GND GND I/O23 I/O22 I/O21 I/O20
Note:
(PLCC/LCC/JLCC packages) pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity.
Rev. 0777I-PLD-4/03
1
Description
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel's proven electrically-erasable technology. The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flipflops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up.
Using the ATF2500C Family's Many Advanced Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are: * * Fully Connected Logic Array - Each array input is always available to every product term. This makes logic placement a breeze. Selectable D- and T-Type Registers - Each ATF2500C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. Buried Combinatorial Feedback - Each macrocell's Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. Selectable Synchronous/Asynchronous Clocking - Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. A Total of 48 Registers - The ATF2500C provides two flip-flops per macrocell - a total of 48. Each register has its own clock and reset terms, as well as its own sum term. Independent I/O Pin and Feedback Paths - Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O's output enable, facilitate true bi-directional I/O design. Combinable Sum Terms - Each output macrocell's three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. Programmable Pin-keeper Circuits - These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled. User Row (64 bits) - Use to store information such as unit history.
*
*
* *
*
*
*
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ATF2500C Family
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during tPR.
Parameter tPR VRST
Description Power-up Reset Time Power-up Reset Voltage
Typ 600 3.8
Max 1000 4.5
Units ns V
Level Forced on Odd I/O Pin during PRELOAD Cycle VIH/V IL VIH/V IL VIH/V IL VIH/V IL
Q Select Pin State Low High Low High
Even/Odd Select Low Low High High
Even Q1 State after Cycle High/Low X X X
Even Q2 State after Cycle X High/Low X X
Odd Q1 State after Cycle X X High/Low X
Odd Q2 State after Cycle X X X High/Low
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Preload and Observability of Registered Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active.
Programming Software Support
All family members of the ATF2500C can be designed with Atmel-WinCUPL TM. ProChip Designer(R) support is expected soon. Check Atmel's web site for the latest version of ProChip. Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the lack of extra grounds on P4 and P26. A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability.
Security Fuse Usage
Bus-friendly Pin-keeper Input and I/O
All ATF2500C family members have programmable internal input and I/O pin-keeper circuits. The default condition, including when using the AT2500C/CQ family to replace the AT2500B/BQ or AT2500H, is that the pin-keepers are not activated. When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last driven state. This ensures that all logic array inputs and device outputs are known states. Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the Software Compiler Mode Selection table for more details. Once the pin-keeper circuits are disabled, normal termination procedures required for unused inputs and I/Os.
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Software Compiler Mode Selection
Device ATF2500C-DIP ATF2500C-PLCC Atmel - WinCupL Device Mnemonic V2500C V2500CPPK V2500LCC V2500CPPKLCC Pin-keeper Disabled Enabled Disabled Enabled
THIRD PARTY PROGRAMMER SUPPORT
Major Third Party Device Programmers support three types of JEDEC files.
Device Description V2500 Cross-programming. JEDEC file compatible with standard V2500 JEDEC file (Total fuses in JEDEC file = 71648). The Programmer will automatically disable the User row fuses and also disable the pin-keeper feature. The Fuse checksum will be the same as the old ATV2500H/L file. This Device type is recommended for customers that are directly migrating from an ATV2500H/L device to an ATF2500C device. V2500B Cross-programming. JEDEC file compatible with standard V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer will automatically disable the User row fuses and also disable the pinkeeper feature. The Fuse checksum will be the same as the old ATV2500B/BQ/BQL/BL file. This Device type is recommended for customers that are directly migrating from an ATV2500B/BQ/BQL/BL device to an ATF2500C device. Programming of User Row bits supported and Pin keeper bit is userprogrammable. (Total fuses in JEDEC file = 71816). This is the default device type and is recommended for users that have Re-compiled their Source Design files to specifically target the ATF2500C device.
ATF2500C (V2500)
ATF2500C (V2500B)
ATF2500C
Note:
The ATF2500C has 71816 Jedec fuses.
Input Diagram
PROGRAMMABLE OPTION
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I/O Diagram
INPUT PROGRAMMABLE OPTION
Functional Logic Diagram Description
The ATF2500C functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.
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ATF2500C Family
Functional Logic Diagram ATF2500C
Notes:
1. Pin 4 and Pin 26 are "ground" connections and are not required for PLCC, LCC and JLCC versions of ATF2500C, making them compatible with ATV2500H, ATV2500B and ATV2500BQ pinouts. 2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND = P33 and P34, and GND = P4, P26 (See Note 1, above).
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Output Logic, Registered(1)
S2 = 0 S1 0 1 1 S0 0 0 1 Terms in D/T1 8 12 8 D/T2 4 4
(1)
Output Configuration Registered (Q1); Q2 FB Registered (Q1); Q2 FB Registered (Q1); D/T2 FB
4
S3 0 1
Output Configuration Active Low Active High
S6 0 1
Q1 CLOCK CK1 CK1 * PIN1
S4 0 1
Register 1 Type D T
S7 0 1
Q2 CLOCK
CK2 CK2 * PIN1
S5 0 1
Register 2 Type D T
Output Logic, Combinatorial(1)
S5 X X X 1 0
S2 = 1 S1 0 0 1 1 1 S0 0 1 0 1 1
Terms in D/T1 4(1) 4 4(1) 4(1) 4 D/T2 4 4 4(1) 4 4 Output Configuration Combinatorial (8 Terms); Q2 FB Combinatorial (4 Terms); Q2 FB Combinatorial (12 Terms); Q2 FB Combinatorial (8 Terms); D/T2 FB Combinatorial (4 Terms); D/T2 FB
Note:
1. These four terms are shared with D/T1.
Clock Option
Note:
1. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
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ATF2500C Family
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40C to +85C Storage Temperature ..................................... -65C to +150C Junction Temperature ............................................. 150C Max Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) Note: *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Operating Temperature VCC Power Supply 0C - 70C (Ambient) 5V 5% Industrial -40C - 85C (Ambient) 5V 10%
Pin Capacitance
f = 1 MHz, T = 25C (1)
Typ CIN COUT Note: 4 Max 6 Units pF Conditions VIN = 0V
8 12 pF VOUT = 0V 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Test Waveforms and Measurement Levels Output Test Load
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AC Waveforms(1) Input Pin Clock
AC Waveforms(1) Product Term Clock
AC Waveforms(1) Combinatorial Outputs and Feedback
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
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ATF2500C
ATF2500C DC Characteristics
Symbol IIL ILO Parameter Input Load Current Output Leakage Current Power Supply Current Standby Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL, VCC = 4.5V VCC = MIN IOL = 8 mA IOL = 6 mA IOH = -100 A IOH = -4.0 mA Com., Ind. Mil. VCC - 0.3 2.4 Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V VCC = MAX, VIN = GND or VCC f = 0 MHz, Outputs Open MIN V CC MAX Com. ATF2500C Ind., Mil. -0.6 2.0 80 130 0.8 VCC + 0.75 0.5 0.5 mA V V V V V 80 Min Typ Max 10 10 110 Units A A mA
ICC
VIL VIH VOL
VOH Note:
1. See ICC versus frequency characterization curves.
ATF2500C AC Characteristics
-15 Symbol tPD1 tPD2 tPD3 tPD4 tEA1 tER1 tEA2 tER2 tAW tAP tAPF Parameter Input to Non-registered Output Feedback to Non-registered Output Input to Non-registered Feedback Feedback to Non-registered Feedback Input to Output Enable Input to Output Disable Feedback to Output Enable Feedback to Output Disable Asynchronous Reset Width Asynchronous Reset to Registered Output Asynchronous Reset to Registered Feedback 8 18 15 Min Max 15 15 11 11 15 15 15 15 12 22 19 Min -20 Max 20 20 15 15 20 20 20 20 Units ns ns ns ns ns ns ns ns ns ns ns
ATF2500C Register AC Characteristics, Input Pin Clock
-15 Symbol tCOS tCFS tSIS tSFS Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time 0 9 9
Min Max Min
-20
Max
Units ns ns ns ns
10 5 0 14 14
11 6
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ATF2500C Register AC Characteristics, Input Pin Clock
-15 Symbol tHS tWS tPS Parameter Hold Time Clock Width Clock Period External Feedback 1/(tSIS + tCOS) FMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tARS Asynchronous Reset/Preset Recovery Time 12
Min Max Min
-20
Max
Units ns ns ns
0 6 12 52 71 83
0 7 14 40 50 71 15
MHz MHz MHz ns
ATF2500C Register AC Characteristics, Product Term Clock
-15 Symbol tCOA tCFA tSIA tSFA tHA tWA tPA Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Width Clock Period External Feedback 1/(tSIA + tCOA) FMAXA Internal Feedback 1/(tSFA + tCFA) No Feedback 1/(tPS) tARA Asynchronous Reset/Preset Recovery Time 8 5 5 5 5 7.5 15 50 58 66 12 Min Max 15 12 10 10 8 10 11 22 33 38 45 Min -20 Max 20 16 Units ns ns ns ns ns ns ns MHz MHz MHz ns
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ATF2500C IV Data 44PLCC
STAND-BY ICC VS. TEMPERATURE (VCC = 5.0V)
ATF2500C OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25C)
ICC (mA)
4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50
100.0 90.0 80.0 70.0 60.0 50.0 -40.0
-10 IOH (mA) -20 -30 -40 4.50
25.0 TEMPERATURE (C)
85.0
STAND-BY ICC VS.
ATF2500C OUTP UT SIN K CU RR EN T VS. SU PPLY V OLTA GE (V O L = 0.5V, T A = 25C )
ICC (mA) 100.0 90.0 80.0 70.0 60.0
4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50
SUPPLY VOLTAGE (TA = 25C)
15 14 IOL (mA) 13 12 11 10 4.50
50.0 4.5 4.8 5.0 5.3 5.5 SUPPLY VOLTAGE (V)
0.0
ATF2500C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, T A = 25C)
INPUT CURRENT (mA)
50 0 -50 -100 -150 -200 -1.4
ATF2500C INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, TA = 25C)
-10.0
IOH (mA)
-20.0
-30.0
-1.2
-1.0
-40.0
-0.8 -0.6 -0.4 INPUT VOLTAGE (V)
-0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
ATF2500C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, T A = 25C)
50 40
40 30 20 10 0 -10 -20 -30 0.0
A TF 2500C INP UT C UR RE NT VS . IN PU T V OL TA GE (V CC = 5.0V, T A = 25C )
IOL (mA)
30 20 10 0
ICC (mA)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INP UT VOL TAG E (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
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0
ATF2500C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, T A = 25C)
TPD NORMALIZED
NORMALIZED TPD VS. SUPPLY VOLTAGE
1.2 1.1 1.0 0.9 0.8 4.50
(TA = 25C)
-2
IOH (mA)
-4
-6
-8
4.5
4.6
4.7
4.8
4.9
5.0
Output Voltage (V)
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
ATF2500C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, TA = 25C)
30 25
NORMALIZED TPD VS. AMBIENT TEMP (VCC = 5V)
1.1 TPD NORMALIZED
1.0
IOL (mA)
20 15 10 5 0
0.9
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.8 -40.0
OUTPUT VOLTAGE (V)
25.0 AMBIENT TEMPERATURE (C)
85.0
100 90
ATF2500C SUPPLY CURRENT VS. SUPPLY VOLTAGE (Freq. = 0 MHz, TA = 25C)
TCOS NORMALIZED
NORMALIZED TCOS VS. SUPPLY VOLTAGE
1.1
(TA = 25C)
ICC (mA)
80 70 60 50
1.0
4.50
4.75
5.00 Supply Voltage (V)
5.25
5.50
0.9 4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
120
ATF2500C SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25C)
1.1 TCOS NORMALIZED
NORMALIZED TCOS VS. AMBIENT TEMP (V CC = 5V)
ICC (mA)
100
1.0
80
0.9
60 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90
0.8 -40.0
25.0 AMBIENT TEMPERATURE (C)
85.0
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NORMALIZED TCOA VS. SUPPLY VOLTAGE
1.3 TCOA NORMALIZED 1.2 1.1 1.0 0.9 0.8 4.50
(T A = 25C)
1.2 TSIS NORMALIZED 1.1 1.0 0.9 0.8 -40.0
NORMALIZED T SIS VS. AMBIENT TEMP (V CC = 5V)
4.75
5.00 SUPPLY VOLTAGE (V)
5.25
5.50
25.0 AMBIENT TEMPERATURE (C)
85.0
NORMALIZED TCOA VS. AMBIENT TEMP (VCC = 5V)
1.1 TCOA NORMALIZED
TSIA NORMALIZED 1.2 1.1 1.0 0.9 0.8 4.50
NORMALIZED TSIA VS. SUPPLY VOLTAGE (T A = 25C)
1.0
0.9
0.8 -40.0
25.0 AMBIENT TEMPERATURE (C)
85.0
4.75
5.00 SUPPLY VOLTAGE (V)
5.25
5.50
NORMALIZED T SIS VS. SUPPLY VOLTAGE
1.2 TSIS NORMALIZED 1.1 1.0 0.9 0.8 4.50
NORMALIZED TSIA VS. AMBIENT TEMP
1.2 TSIA NORMALIZED 1.1 1.0 0.9 0.8 -40.0
(TA = 25C)
(VCC = 5V)
4.75
5.00 SUPPLY VOLTAGE (V)
5.25
5.50
25.0 AMBIENT TEMPERATURE (C)
85.0
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Ordering Information
tPD (ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code
ATF2500C-15JC 15 10 52 ATF2500C-15JI ATF2500C-20JC ATF2500C-20PC 20 11 40 ATF2500C-20JI ATF2500C-20PI 44J 40P6 Industrial (-40C to 85C) 44J 44J 40P6 Industrial (-40C to 85C) Commercial (0C to 70C)
Package
44J
Operation Range
Commercial (0C to 70C)
Package Type 40P6 44J
40-pin, 0.600" Wide, Plastic, Dual Inline Package (PDIP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
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Packaging Information
44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
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40P6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B
R
18
ATF2500C
0777I-PLD-4/03
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
(c) Atmel Corporation 2003. All rights reserved. Atmel(R) and combinations thereof, and ProChip Designer (R) are the registered trademarks, and Atmel-WinCUPL TM is the trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0777I-4/03/0M
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Printed on recycled paper.

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